A：The potential revenue growth could be substantial, with an objective set for a $1 million dollar realization in Q4 if a significant contract is awarded as forecasted. The company has a high level of confidence in winning this contract, which could otherwise push into Q1 2026 affecting Q4 revenue figures.

A：The SRH FPGA test chip is critical to the company's strategy as it aids in securing strategic design wins and accelerating the storefront business model. The demonstration of the test chip is expected to increase enthusiasm and accelerate order commitments from defense and industrial base entities. It also enables the company to showcase the capability of its eFPGA hard IP for ASIC applications and meets program requirements ranging from radiation tolerance to strategic radiation-hardening.

A：The company differentiates its offering by being the only source for strategic radiation-resistant FPGAs and eFPGA hard IP that is fabricated in the U.S. by a U.S. company, as per government contracts requiring onshore fabrication. The company's capability to design with the Aurora FPGA user tools for both SRH discrete FPGAs and eFPGA hard IP in AICC designs is also emphasized as a significant advantage.

A：Revenue recognition from the current tranche is expected to be low in Q3, with a significant rebound in Q4 and an increase in quarterly revenue recognition in 2026 funded by the next tranche.

A：The company has already delivered customer-specific eFPGA heart IP for the customer's first Intel 18 A test ship. An allocation of test ships from a previous contract is expected during Q1 2026 for internal verification and characterization, and a mid A six-figure contract for a second Intel At test chip was also awarded.

A：The new feasibility contract is for a 1 million less feasibility study that is scheduled for delivery next week. It aims to enable the customer to tape out a very high-density in late 2026. The architectural changes implemented in this feasibility study can be leveraged across all advanced fabrication nodes down to 12 nm, significantly expanding the market for eFPGA hard IP and discrete devices.

A：The Digital Proof of Concept Shiplet program is a strategy to accelerate the storefront shiplet initiative. The initial phase of the digital FPGA Shiplet POC, which connects eFPGA IP to UIE IP and interface logic, has been completed. This phase is now available for further development to meet different customer requirements and is engaging with prospective customers across various markets.

A：The new $1 million eFPGA hard IP contract is for a high-performance data center ASIC fabricated on TSMC's 12 nm process. The contract highlights the need for larger blocks of eFPGA, the increasing value of eFPGA in customer designs, winning contracts for advanced fabrication processes, and growing success in commercial market sectors.

A：The company is expanding its involvement with Adib, which specializes in cybersecurity for strategic and tactical weapons systems. The company will provide Adib with eFPGA hard IP for their secure system-on-chip processors, emphasizing the enhanced security only eFPGA can provide.

A：The company has entered into an eFPGA hard IP contract with a new defense industrial base customer valued at $1.1 million, which will be fabricated on the GF 1LAP process. This contract involves utilizing a large block of eFPGA hard IP for critical functions, and the company will provide test chips for an evaluation kit compatible with common third-party development environments.

A：The company's total third-quarter revenue was $2 million, aligned with the midpoint of guidance. New product revenue was $1 million, mature product revenue was $1.1 million, non-GAAP gross margin was -11.9%, non-GAAP operating expenses were approximately $2.9 million, and non-GAAP net loss was $3.2 million or 19 cents per diluted share. At the end of Q3, total cash was $17.3 million, inclusive of $15 million from a $20 million credit facility.

A：The expected total revenue for the fiscal fourth quarter is $6 billion. Factors that could affect it include the potential contract award of nearly $3 million for a commercial application which could be awarded late in the quarter, impacting the revenue recognition for that period.

A：The expected non GAAP gross margin for Q4 is approximately 45% at $3.5 million of revenue and 68% at $6 million of revenue. The non GAAP operating expenses for Q4 are expected to be approximately $3 million plus or -5%.

A：The projected non GAAP net loss for Q4 is approximately $1.9 million for a loss of 11 cents per share at the low end of the revenue range, and a non GAAP net profit of approximately $600,000 or 4 cents per share at the high end of the revenue range.

A：The industry trends driving the increased interest in FPGA technology include smart systems that rely on algorithms for intelligence, which can be processed faster and with lower power consumption in hardware. Hardware is also more secure against cyber threats. Additionally, sophisticated smart systems designs target advanced fabrication nodes, requiring longer life cycles, adaptability to changing algorithms, and environmental compliance.

A：The use of EFPGA in ASIC designs benefits the design life cycle and program managers by providing adaptability to changing algorithms, evolving functional requirements, and external changes, thus lengthening the life cycle of ASIC designs. This flexibility allows program managers to move ASICs to production more quickly and with lower risk, which shortens design cycles and lowers development costs.

A：The purpose of the internally funded development of an SRH (SRI International) FPGA test chip is to address a range of environmental requirements from radiation tolerance to strategic compliance. This development is designed to accelerate design wins and optimize the company's position in discrete FPGA designs, using the same onshore 12nm fabrication process as used for SRI's ASICs.

A：The speaker notes that programmable logic has been a significant part of the defense industrial base for decades and this demand is not changing, with approximately 75% of defense systems incorporating programmable logic and a large percentage of the total semiconductor spend by the DoD.

A：The speaker indicates that there are no delays with current programs on contract and if there's a delay in funding, the company is prepared with cash reserves. If there's no delay, they anticipate good positive cash flow for the quarter.

A：The speaker notes that new Rfis, rfss, or Rfps from the government for various development programs were paused due to furloughs. However, they do not anticipate these delays being permanent and expect that once government funding is restored and people return from furlough, the programs will resume.

A：The speaker anticipates that the storefront revenue associated with developments discussed will be significant, targeting a range around 10% of total revenue without providing an exact number. Factors driving upside include strong demand for their technology and projects under development, public interest in strategic defense system modernization, and the need for radiation tolerance in various programs. Downside could be driven by factors not specified in the transcript.

A：The GDF Hastelloy process allows for the development of FPGAs and ASICs. For 12 o'clock process, which is commonly used by the defense industrial base, there is a significant amount of available IP and test data due to government funding. This process is known to be risk-averse and well-understood, which is beneficial for creating ASICs and FPGAs. The company plans to license their IP for ASIC development, which could lead to back-end royalty opportunities. In the near term, they aim to monetize these opportunities to generate several million dollars a year. For devices, the introduction of a strategic Red Hart FPGA could provide a significant step function increase in revenue potential due to higher average selling prices (ASP) compared to royalties. The strategy involves licensing the technology broadly and capturing revenue from this strategic Red Hart FPGA.

A：Brian believes that the opportunity with the 12nm process, due to its strategic nature and IP licensing options, is a larger opportunity compared to Gfs 12 LP and other founders' projects. The 12nm process allows for denser transistors and higher functionality, increasing the value of the parts. He highlights the potential to address customer needs without requiring a custom ASIC, which could save the customer or government significant development costs and time.

A：The strategic importance of the 12nm process for the new dev kits lies in the capability to implement a lot of functionality on the FPGAs, potentially allowing customers to avoid the need for custom ASICs. This can result in significant cost savings and development time reduction for the government and customers. The process enables high capability on the FPGAs, which is expected to lead to substantial revenue generation for the company.

A：While Brian does not provide specific numbers, he indicates that the number of development kits and customers will be sufficient to generate a significant revenue number, not just a rounding figure on the income statement. The company has intentionally budgeted enough resources to provide customers with the tools to test the devices, both in development kits and on their own devices.

A：The typical design cycle for customers after receiving development kits involves a cautious and risk-averse community that wants to conduct their own testing. This usually takes several quarters to complete, including environmental tests and exercising the design.

A：The target for customers is to reach Technology Readiness Level (TRL) 5, which is when they can successfully run the part through rigorous testing that simulates the operational environment. The company hopes to support customers to achieve this by mid-next year, after which point they can transition into programs of record.

A：The company plans to make critical hires and allocate expenses accordingly as they transition from test chips to actual product chips. They aim to be mindful of financial considerations, align investments with customer needs, and potentially involve customers in the investment process to ensure alignment. With the new hires, the expectation is to maintain Opex around $3.5 million per quarter starting from Q2 onwards.

A：The anticipated share count for 2025 is 17,090,000 shares, which are all currently outstanding. The revenue forecast suggests a decline of 20% to 30% from 2024, which is a change from the previously mentioned modest decline. The change is attributed to large IP contract values that, when they do not occur in the fiscal year, cause significant changes in revenue percentage compared to the current levels. With more high-value contracts expected in the future, the revenue fluctuations are anticipated to be less pronounced.